This week on the IEEE Electronic Components and Packaging Technology Conference, Intel unveiled that it’s growing new chip packaging know-how that may enable for larger processors for AI.
With Moore’s Regulation slowing down, makers of superior GPUs and different information middle chips are having so as to add extra silicon space to their merchandise to maintain up with the relentless rise of AI’s computing wants. However the most dimension of a single silicon chip is mounted at round 800 sq. millimeters (with one exception), so that they’ve needed to flip to advanced packaging technologies that combine a number of items of silicon in a means that lets them act like a single chip.
Three of the improvements Intel unveiled at ECTC have been aimed toward tackling limitations in simply how a lot silicon you’ll be able to squeeze right into a single bundle and the way massive that bundle might be. They embody enhancements to the know-how Intel makes use of to hyperlink adjoining silicon dies collectively, a extra correct methodology for bonding silicon to the bundle substrate, and system to broaden the scale of a important a part of the bundle that take away warmth. Collectively, the applied sciences allow the combination of greater than 10,000 sq. millimeters of silicon inside a bundle that may be larger than 21,000 mm2—an enormous space concerning the dimension of 4 and a half credit cards.
EMIB will get a 3D improve
One of many limitations on how a lot silicon can slot in a single bundle has to do with connecting numerous silicon dies at their edges. Utilizing an natural polymer bundle substrate to interconnect the silicon dies is essentially the most reasonably priced choice, however a silicon substrate lets you make extra dense connections at these edges.
Intel’s answer, launched greater than 5 years in the past, is to embed a small sliver of silicon within the natural bundle beneath the adjoining edges of the silicon dies. That sliver of silicon, known as EMIB, is etched with superb interconnects that improve the density of connections past what the natural substrate can deal with.
At ECTC, Intel unveiled the newest twist on the EMIB know-how, known as EMIB-T. Along with the standard superb horizontal interconnects, EMIB-T offers comparatively thick vertical copper connections known as through-silicon vias, or TSVs. The TSVs enable energy from the circuit-board beneath to instantly connect with the chips above as an alternative of getting to route across the EMIB, decreasing energy misplaced by an extended journey. Moreover, EMIB-T accommodates a copper grid that acts as a floor aircraft to cut back noise within the energy delivered on account of course of cores and different circuits abruptly ramping up their workloads.
“It sounds easy, however this can be a know-how that brings loads of functionality to us,” says Rahul Manepalli, vice chairman of substrate packaging know-how at Intel. With it and the opposite applied sciences Intel described, a buyer may join silicon equal to greater than 12 full dimension silicon dies—10,000 sq. millimeters of silicon—in a single bundle utilizing 38 or extra EMIB-T bridges.
Thermal management
One other know-how Intel reported at ECTC that helps improve the scale of packages is low-thermal-gradient thermal compression bonding. It’s a variant of the know-how used at present to connect silicon dies to natural substrates. Micrometer-scale bumps of solder are positioned on the substrate the place they’ll connect with a silicon die. The die is then heated and pressed onto the microbumps, melting them and connecting the bundle’s interconnects to the silicon’s.
As a result of the silicon and the substrate broaden at totally different charges when heated, engineers need to restrict the inter-bump distance, or pitch. Moreover, the growth distinction makes it troublesome to reliably make very massive substrates stuffed with plenty of silicon dies, which is the path AI processors must go.
The brand new Intel tech makes the thermal growth mismatch extra predictable and manageable, says Manepalli. The result’s that very-large substrates might be populated with dies. Alternatively, the identical know-how can be utilized to extend the density of connections to EMIB right down to about one each 25 micrometers.
A flatter warmth spreader
These larger silicon assemblages will generate much more warmth than at present’s methods. So it’s important that the warmth’s pathway out of the silicon isn’t obstructed. An built-in piece of steel known as a warmth spreader is essential to that, however making one large enough for these massive packages is troublesome. The bundle substrate can warp and the steel warmth spreader itself won’t keep completely flat; so it won’t contact the tops of the new dies it’s presupposed to be sucking the warmth from. Intel’s answer was to assemble the built-in warmth spreader in elements as an alternative of as one piece. This allowed it so as to add further stiffening elements amongst different issues to maintain all the things in flat and in place.
“Maintaining it flat at larger temperatures is a giant profit for reliability and yield,” says Manepalli.
Intel says the applied sciences are nonetheless within the in R&D stage and wouldn’t touch upon when these applied sciences would debut commercially. Nonetheless, they’ll possible need to arrive within the subsequent few years for the Intel Foundry to compete with TSMC’s planned packaging expansion.
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