Reinforcement Learning Uncovers Silent Data Errors

For prime-performance chips in huge data centers, math could be the enemy. Because of the sheer scale of calculations occurring in hyperscale data centers, working around the clock with hundreds of thousands of nodes and huge quantities of silicon, extraordinarily unusual errors seem. It’s merely statistics. These uncommon, “silent” knowledge errors don’t present up throughout standard quality-control screenings—even when corporations spend hours in search of them.

This month on the IEEE International Reliability Physics Symposium in Monterey, Calif., Intel engineers described a method that uses reinforcement learning to uncover extra silent knowledge errors quicker. The corporate is utilizing the machine learning technique to make sure the standard of its Xeon processors.

When an error occurs in a knowledge middle, operators can both take a node down and exchange it, or use the flawed system for lower-stakes computing, says Manu Shamsa, {an electrical} engineer at Intel’s Chandler, Ariz., campus. However it will be significantly better if errors might be detected earlier on. Ideally they’d be caught earlier than a chip is integrated in a pc system, when it’s attainable to make design or manufacturing corrections to forestall errors recurring sooner or later.

“In a laptop computer, you received’t discover any errors. In knowledge facilities, with actually dense nodes, there are excessive probabilities the celebs will align and an error will happen.” —Manu Shamsa, Intel

Discovering these flaws shouldn’t be really easy. Shamsa says engineers have been so baffled by them they joked that they should be because of spooky motion at a distance, Einstein’s phrase for quantum entanglement. However there’s nothing spooky about them, and Shamsa has spent years characterizing them. In a paper introduced on the identical convention final yr, his workforce gives an entire catalog of the causes of those errors. Most are because of infinitesimal variations in manufacturing.

Even when every of the billions of transistors on every chip is purposeful, they don’t seem to be fully an identical to at least one one other. Refined variations in how a given transistor responds to modifications in temperature, voltage, or frequency, for example, can result in an error.

These subtleties are more likely to crop up in enormous knowledge facilities due to the tempo of computing and the huge quantity of silicon concerned. “In a laptop computer, you received’t discover any errors. In knowledge facilities, with actually dense nodes, there are excessive probabilities the celebs will align and an error will happen,” Shamsa says.

Some errors may crop up solely after a chip has been put in in a knowledge middle and has been working for months. Small variations within the properties of transistors could cause them to degrade over time. One such silent error Shamsa has discovered is said to electrical resistance. A transistor that operates correctly at first, and passes normal assessments to search for shorts, can, with use, degrade in order that it turns into extra resistant.

“You’re pondering all the things is okay, however beneath, an error is inflicting a improper choice,” Shamsa says. Over time, because of a slight weak spot in a single transistor, “one plus one goes to a few, silently, till you see the influence,” Shamsa says.

The brand new method builds on an current set of strategies for detecting silent errors, referred to as Eigen tests. These assessments make the chip do arduous math issues, repeatedly over a time period, within the hopes of creating silent errors obvious. They contain operations on completely different sizes of matrices crammed with random knowledge.

There are a lot of Eigen assessments. Operating all of them would take an impractical period of time, so chipmakers use a randomized strategy to generate a manageable set of them. This protects time however leaves errors undetected. “There’s no precept to information the collection of inputs,” Shamsa says. He needed to discover a strategy to information the choice so {that a} comparatively small variety of assessments may flip up extra errors.

The Intel workforce used reinforcement learning to develop assessments for the a part of its Xeon CPU chip that performs matrix multiplication utilizing what are referred to as fuse-multiply-add (FMA) directions. Shamsa says they selected the FMA area as a result of it takes up a comparatively massive space of the chip, making it extra weak to potential silent errors—extra silicon, extra issues. What’s extra, flaws on this a part of a chip can generate electromagnetic fields that have an effect on different components of the system. And since the FMA is turned off to avoid wasting energy when it’s not in use, testing it entails repeatedly powering it up and down, probably activating hidden defects that in any other case wouldn’t seem in normal assessments.

Throughout every step of its coaching, the reinforcement-learning program selects completely different assessments for the possibly faulty chip. Every error it detects is handled as a reward, and over time the agent learns to pick which assessments maximize the possibilities of detecting errors. After about 500 testing cycles, the algorithm realized which set of Eigen assessments optimized the error-detection charge for the FMA area.

Shamsa says this method is 5 occasions as prone to detect a defect as randomized Eigen testing. Eigen assessments are open source, a part of the openDCDiag for knowledge facilities. So different customers ought to be capable of use reinforcement studying to change these assessments for their very own methods, he says.

To a sure extent, silent, delicate flaws are an unavoidable a part of the manufacturing course of—absolute perfection and uniformity stay out of attain. However Shamsa says Intel is attempting to make use of this analysis to study to search out the precursors that result in silent knowledge errors quicker. He’s investigating whether or not there are pink flags that might present an early warning of future errors, and whether or not it’s attainable to vary chip recipes or designs to handle them.